CCmulation

Mixed-signal verification for hardware teams

Verilog and SPICE in one browser workspace

Run mixed-signal verification with tenant isolation and team invites — built for hardware startups and product teams.

Start evaluationBook demo
cmulation — run #4821
Sim-Credits
128
Runtime
1.8s
Storage
42 MB
Waveform outputpassed
Run summary

Completed — VCD waveforms and full simulator logs captured. Open the run to review the $display output and confirm pass/fail.

Cloud simulation

Verilog + SPICE in one workspace

  • Upload digital and analog designs — single files or multi-file archives with a named top module or cell.
  • Managed simulators run jobs in a browser-native tenant workspace — no local toolchain to install.
  • Review VCD waveforms, full logs, and clear pass/fail the moment verification finishes.
cmulation — new simulation

Drop .v, .sp, or .zip archive

Top module or cell name required for archives

counter_tb.v

Verilog testbench

4.2 KB

dut_counter.v

Top module: counter

1.8 KB
Managed simulator
running

Icarus Verilog · managed cloud worker

Diagnostic AI

On the roadmap

Understand failures, not just read logs

  • Plain-language diagnostics that turn dense simulator output into clear next steps, tied to each run.
  • We are holding it until our privacy review completes — your designs, and the models that read them, deserve that care.
  • Not part of the product today. Everything else on this page is available now.

Projects & teams

Tenant controls for product teams

  • Group related runs into projects to keep mixed-signal verification organized.
  • Invite teammates with owner, admin, and member roles — built for hardware startups and teams of 5–20 engineers.
  • Each workspace is tenant-isolated with plan-aware entitlements and least-privilege access.
cmulation — ACME Mixed-Signal
RTL Verification
tenant isolated
counter_tb.v
pll_lock.sp
adc_driver.v

Team members

You
Owner
Priya S.
Admin
Alex K.
Member

Run history

Auditable history for every run

  • Each run is recorded with status, timing, logs, and waveforms.
  • Revisit any past simulation at any time.
  • Reliable history for design reviews, handoffs, and reproducible verification.
cmulation — run history
Search runs, logs, or waveforms…
#4821 · counter_tb.v

1.8s runtime · 2 min ago

passed
#4819 · pll_lock.sp

2.1s runtime · 1 hr ago

failed
#4815 · uart_rx.v

0.9s runtime · Yesterday

passed
#4802 · adc_driver.v

3.4s runtime · Yesterday

passed

Waveforms and full logs saved with every run

Evaluate Cmulation with your team

Create a free evaluation workspace or book a walkthrough for Pro, Pro+, or design-partner plans. Recurring subscriptions are coming soon.

Start evaluationBook demo